In recent years, a technique for forming a thin film transistor (TFT) by using a semiconductor thin film (having a thickness of approximately several nanometers to several hundred nanometers) formed over a substrate having an insulating surface has attracted attention. Thin film transistors are applied to a wide variety of electronic devices such as ICs or electro-optical devices, and their development especially as switching elements for an image display device has been accelerated.
Moreover, there is a trend in an active matrix semiconductor device typified by a liquid crystal display device towards a larger screen, e.g., a 60-inch diagonal screen, and further, the development of an active matrix semiconductor device is aimed even at a 120-inch diagonal screen or a larger screen. In addition, a trend in resolution of a screen is toward higher definition, e.g., high-definition (HD) image quality (1366×768) or full high-definition (FHD) image quality (1920×1080), and development of a so-called 4K Digital Cinema display device, which has a resolution of 3840×2048 or 4096×2180, is also accelerated.
An increase in screen size or definition tends to increase wiring resistance in a display portion. An increase in wiring resistance causes delay of signal transmission to an end portion of a signal line, voltage drop in a power supply line, or the like. As a result, deterioration of display quality, such as display unevenness or a defect in grayscale, or an increase in power consumption is caused.
In order to suppress an increase in wiring resistance, a technique of forming a low-resistance wiring layer using copper (Cu) is considered (e.g., see Patent Documents 1 and 2).    [Patent Document 1] Japanese Published Patent Application No. 2004-133422    [Patent Document 2] Japanese Published Patent Application No. 2004-163901